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| 4000 SERIES Acapella Optical Modem IC ACS411CS Main Features * * * Three chip set supporting full duplex serial transmission over twin optical fiber, one fiber with WDM. * * * * Incorporates 2 x 256kbps maintenance channels with optionof multi channel operation with a framing signal. * * AC Processor Link budgets of 27dB with Laser + PIN on single mode fiber. Conforms to all jitter attenuation, jitter transfer and input jitter tolerance specification defined by AT&T, ITU-T and Bellcore recommendations. Bit Error Rate (BER) of < 10-10 ACS9020 available in 64 pin TQFP and ACS4110 available in 176 pin TQFP package. ACS411CS 8 bit parallel bus interface device setup mode contr ol Tx data status Rx data status status reset S4 TPOS1/TNEG1 TPOS16/TNEG16 RPOS1/RNEG1 RPOS16/RNEG16 TCLK(16:1) RCLK(16:1) TmD1/RmD1 TmD2/RmD2 TmCLK/RmCLK Select between NRZ and pseudo-bipolar HDB3/AMI/B3ZS/ B6ZS/B8ZS input data coding types. 11 C Twin Fiber Link 16 transmit data channels 16 receive data channels 16 transmit data clocks 16 receive data clocks 2 transmit maint. channels 2 receive maint. channels 1 transmit maint. clock 1 receive maint. clock Up to 16 independent synchronous data channels. 1 x OC1 (STS1) @ 51.840Mbps 1 x E3/T3 4 x E2, 7 x T2 16 x E1/T1 ACS411CS device setup mode contr ol Tx data status Rx data status status reset S 8 bit parallel bus interface RPOS1/RNEG1 RCLK(16:1) TCLK(16:1) RmD1/TmD1 RmD2/TmD2 RmCLK/TmCLK Configurable parallel microprocessor bus interface. LIU interface RPOS16/RNEG16 TPOS1/TNEG1 TPOS16/TNEG16 16to1 Mux 1to16 Mux 1to16 Mux 16to1 Mux Twin fiber full duplex system using ACS411CS chip set with external T1/E1 Framer ICs and microprocessor. General Description The ACS411CS is a complete controller, driver and receiver chipset supporting full-duplex synchronous transmission up to 51.840Mbps over single/twin optical fiber. The designer can share the available bandwidth over 1 to 16 main channels. In addition to the main channels, the ACS411CS provides two independent maintenance channels with a data rate selectable up to 256kbps. On the electrical side the ACS411CS has a selectable interface for either NRZ or the pseudo bipolar data coding types HDB3/AMI/B3ZS/B6ZS/B8ZS. The ACS411CS has a parallel microprocessor bus interface. This can be used for device set-up, diagnostics, control and status analysis. Additional flags for Tx data status, Rx data status and alarm indication for both near end and far end receive fail are accessible via the uP interface. Communicating modems automatically maintain synchronization with each LIU interface Processor Acapella Optical Modem IC The ACS411CS comprises a chip set of two/three (link budget dependent) highly integrated devices, the ACS9020 and ACS4110. The ACS9020 is an analogue device and the ACS4110 is predominately a digital device. The ACS9020 contains the Laser/LED driver as well as the PIN receiver circuitry. Since the devices are transmitting and receiving continuously, for long haul applications two ACS9020 devices are required, one configured as the transmitter and the other configured as the receiver. The ACS4110 comprises the logic necessary to time compress and decompress the data, plus clock recovery and all the logic associated with valid data transmission and reception and locking status. The ACS4110 also has a configurable parallel microprocessor bus interface for device configuration (control) and status analysis. The device setup is also possible via the far end (remote control) or directly via pins for the basic device setup. For the purpose of this specification the chip-set will be referred to as the ACS411CS and the individual devices as the ACS9020 or ACS4110. ACS411CS PORB The Power On Reset (PORB) pin resets the device if forced low for 2ms or more. In normal operation PORB should be held High. It is recommended that PORB is connected to VD+ via a 100K resistor and to GND via a 100nF capacitor. System Clock The system clock on the ACS411CS is derived locally using the on-chip crystal oscillator and multiplying PLL. The oscillator (XTO/I) requires the use of a fundamental parallel resonance crystal with appropriate padding capacitors. The crystal specification should be: Calibration tolerance: +/- 20ppm @ 25C Temp. tolerance: +/-20ppm @ -40 to +85C -40 to +85C in Load condition: Mode 1 2 3 4 5 Temperature range: For applications requiring a higher link budget (up to 30dB) a three chip solution has to be used, where the laser driver and PIN receiver circuitry are separated. Inter-Modem Coding el im 2 For low link budget applications (up to 10dB) two chips, the ACS9020 analogue IC (including laser driver and PIN receiver circuitry) and the ACS4110 are sufficient. Padding capacitor: The system clock defines the burst frequency at which data is transmitted over the optical link via the optical interface. The receive circuitry within the ACS4110 recovers the clock from the received data at the RXDAT inputs and produces a clock that is synchronised to the incoming data stream. The system clock must have a maximum tolerance of +/50ppm over the desired temperature range. The inter-IC coding between communication modems is 8B10B. Whilst transparent to the user, 8B10B encoding ensures that there is no DC component in the signal, and provides frequent data transitions, factors which ease the task of data recovery and clock extraction. The coding rules are continuously checked to ensure the integrity of the link, and errors are indicated on the ERRL and ERRC pins (see section headed ERRC and ERRL - Error Detection ). Pr Optical Operational Modes The ACS411CS has four optical operational modes, all supporting twin fiber. The ACS9020 can also utilise Lasers/LED and PIN combinations, including a PIN with an internal Trans-Impedence Amplifier (TIA) controlled by PINRX. The twin fiber Laser modes in Table 1 may be converted to single fiber operation simply by interfacing to Wave Division Multiplexer (WDM) device indicated by mode 5. Transmit and Receive functions Data presented at the near-end TPOS/TNEG is timecompressed, encoded in the 8B10B format and transmitted over the fiber link to the far end receiver. Similarly, data presented at the far-end TPOS/TNEG is time-compressed, encoded in the 8B10B format and transmitted over the other fiber link to the near end. ACS411CS PRE-RELEASE Issue 6.0 July 1999. ar Optical Device Laser and PIN diode without TIA. Laser and PIN diode with integrated TIA. LED and PIN diode without TIA. LED and PIN diode diode with integrated TIA. WDM Table 1: Optical modes y parallel load 15pF 18-22pF (tune for desired tolerance) Mode 1 - Laser & PIN without integrated TIA In mode 1, the device is configured for use with a Laser and a PIN Diode without a TIA. In this configuration it is important to employ the TIA available within the ACS9020. The ACS9020 TIA is activated by setting PINRX = High. In this configuration, the PIN Diode should be connected to the PINP/PINN pins so that the TIA/ Post-Amp combination on the ACS9020 is used. In this configuration, the PIN Diode should be connected to the PINP/PINN pins so that the TIA/ Post-Amp combination on the ACS9020 is used. LED LAP Fiber LAN PIN Diode PINP Laser LAP Fiber PINN Fiber PMN LAN Mode 3: LED and PIN. PINP PINN Mode 1: 3-pin Laser and PIN. Mode 2 - Laser and & PIN Receiver with a TIA. el im Laser Fiber PIN Diode Fiber In mode 2, the device is configured for use with a Laser and PIN Diode with an integrated TIA (Pin Receiver). In this mode it is important to bypass the TIA on the ACS9020 device.The VP/VN inputs are activated by setting PINRX = Low. in VP VN In mode 4, the device is configured for use with an LED and PIN Diode with an integrated TIA (Pin Receiver). In this mode it is important to bypass the TIA on the ACS9020 device.The VP/VN inputs are activated by setting PINRX = Low. In this mode, the outputs from the PIN Receiver should be connected directly to the VP/VN inputs of the ACS9020 Post-Amp via AC coupling capacitors as shown in the diagram below. In this mode, the outputs from the PIN Receiver should be connected to the VP/VN inputs of the ACS9020 Post-Amp via AC coupling capacitors as shown in the diagram below. ar LED LAP LAN 100PF Fiber Mode 4 - LED & PIN with a TIA. y Fiber PIN Diode + PIN Diode Pr Fiber 100PF LAP LAP - PMN LAN Mode 4: LED and PIN with internal TIA. 100PF + VP VN 100PF Mode 5 - WDM Bidirectional Device The device can be configured for use with a WDM device (with and without a TIA) to realise a single fiber link. The electrical connections are the same as those for mode1 and mode2 dependent on whether the WDM bidirectional device has a TIA included or not. If the device has a TIA integrated then the receivers Positive/Negative differential outputs are connected to VP/VN respectively via AC coupling capacitors with PINRX set Low. - Mode 2: 4-pin Laser and PIN with integrated TIA. Mode 3- LED & PIN without integrated TIA In mode 3, the device is configured for use with a LED and a PIN Diode without a TIA. In this configuration it is important to employ the TIA available within the ACS9020. The ACS9020 TIA is activated by setting PINRX = High. 3 ACS411CS PRE-RELEASE Issue 6.0 July 1999. Wave Division Multiplexing Device Laser LAP I (LAN) = I (BIAS) + I (MOD) <= 100 mA PMN LAN The bias current and modulation currents should be set to give the appropraite extinction ratio. The extinction ratio is the ratio of the optical high power compared to the optical low power. Single Fiber PIN Diode PINP/VP PINN/VN Eg. An extinction ratio of 13db, is where the optical high power is 20 times the optical low power. Control of LASER Current To minimise switching the delay, a permenent bias current is maintained through the LASER. A second current source called the modulation current varies the intensity of the output light power such that: Optical Low current = Bias current. Optical high current = Bias current + Modulation current WDM device containing 3-pin Laser and PIN. If the device does not have an integrated TIA then the PIN Diodes's Cathode/Anode is connected to PINP/PINN respectively with PINRX set High. Control of LED Current To minimise the switching delay, a permenent bias current is maintained through the LED. A second current source called the modulation current varies the intensity of the output light power such that: Optical Low current = Bias current. Optical high current = Bias current + Modulation current Pr (MOD) = 100/ RRMODSET The bias current is determined by a resistor connected between pin RBIASSET and Ground.The bias current can be calculated from the formula below: el im 4 Unlike Lasers, LED's have a linear relationship between current and output light power. Also, the output power of LEDs does not vary significantly with temperature. Therefore, LEDs are driven with a predetermined biased current and modulation current fixed by the resistors between RBIASET and GND and RMODSET and GND respectively. In order to fix the modulation current the signal MODFIX should be set = High. For Lasers, there is a non-linear relationship between the output power and the applied current. In addition, Laser output power will vary significantly with temperarure for a constant current. For these reason Laser drive current must be controlled so as to maintain a constant optical output power from the Laser. The monitor pin resident in the laser converts the incident light power (typically leaked from the rear facet of the laser itself) to a monitor current, which is directly compared to a preset programmed current (the current flowing through RMODSET). The Laser drive current is automatically adjusted to maintain the original preset light level over the temperature and voltage range. The designer should be aware that whilst the control loop maintains the current generated by the monitor-pin within a tolerance of 2%, there is additional uncertainty attributed to the monitor-pin's temperature coefficient of responsivity. Data relating to the Laser characteristics should be acquired from the Laser supplier. The bias current is set in the same way as it is for the LED driver. The bias current is determined by a resistor connected between pin RBIASSET and GND. The bias current can be calculated from the formula below: I (LAN) (BIAS) = 50/ RRBIASSET I = Amps Where R RBIASSET > 1Kohm, tolerance +/- 20% The modulation current is determined by a resistor connected between pin RMODSET and Ground.The modulation current can be calculated from the formula below: I (LAN) Where R RMODSET > 1Kohm, tolerance +/- 20% I = Amps When setting the bias current and the modulation current it is important to ensure that the sum of the component currents do not exceed 100 mA. ACS411CS PRE-RELEASE Issue 6.0 July 1999. in I (LAN) Where R RBIASSET > 1Kohm, tolerance +/- 20% I = Amps Whilst the bias current flowing through the Laser is fixed, the modulated component is automatically regulated to maintain a near constant output light power. In order to activate the automatic regulation of the modulation current it is important that the pin MODFIX is set Low. The monitor-pin current is set by a variable resistor (R RMODSET) connected between pin RMODSET and Ground. Acapella recommends that RRMODSET should comprise a logarithmic potentiometer of value 50 ar (BIAS) = 50/ RRBIASSET y Kohms. It is important that RRMODSET is inserted and adjusted to its maximum resistance value of 50 Kohms prior to applying power to the ACS9020 for the first time and prior to following the procedure detailed in section headed, Laser Adjustment Procedure. Start be setting the current control resistors RRMODSET and RRBIASSET to their highest values (at least 50Kohm is recommended). The bias current is then set to the desired level by adjusting the variable resistor RRBIASSET. Since the bias current sets the optical low-level for the Laser, it is essential that the Laser driver data inputs are set at a continuous logic low level. The resistor value (typically a 50K potentiometer) is reduced until the desired bias current is achieved or until the desired low-level optical output power is achieved. It should be understood that since the bias current is fixed (not regulated), the low level optical output power will vary across the temperature and voltage range. Once the bias current is set, the modulation current maybe set by adusting the variable resistor RRMODSET. The automatic power regulation circuitry for the modulation current maintains the average optical output power and not the peak power. For this reason, during the set-up process in the absence of the appication data, it is recommended that the Laser driver is stimulated with a square wave. Most application data used in fiber optic transmission is dc-balanced (equal number of ones and zeros), so a square-wave is an accurate representation of the real data. The resistor value (typically a 50K potenmtiometer) is reduced until the desired optical-high ouput power is achieved. The modulation ouput power will then be regulated such that the average ouput optical output power (bias + modulation) is mainatined over the recommended temperature and voltage range. I(PMN - AVERAGE) (BIAS + MOD) = 1/ RRMODSET Where RRMODSET > 1Kohm, tolerance +/- 20% TXMON and TxFLG TXMON is used to monitor the current delivered to the LED or Laser. TXMON is a current source that proportionally mirrors the current flow through the LED or Laser. By placing an appropriate external resistor RTXMON between TXMON and GND, the voltage developed (referenced to GND), will be proportional to the transmit current. During the Laser setup procedure TXMON should be monitored to ensure that the Laser manufacturer's maximum current specification is not exceeded. The transmit current monitor is a current source flowing from VDD out of pin TXMON. This current is representative of the Laser/LED drive current. ITXMON = I BIAS/50 + IMOD/100 IBIAS is the Low level bias current. Average drive current, IAVG = (IBIAS + IMOD) /2 Therefore ITXMON = IAVG/50 el im 5 IMOD is the peak Modulation level bias current. The average modulation current is half this value. Pr TXMON may also be employed during normal operation to continuously check the Laser current. The voltage developed across RTXMON is compared within an internally generated reference voltage of 1.25V. In the event that the reference voltage is exceeded, the TXFLAG is set High, otherwise it is set Low. In this way, the value of resistor on TXMON can be chosen to activate TXFLAG at any desired transmit current e.g. If RTXMON = 1KW, then TXFLAG will be set if IAVG exceeds 62.5mA. If desired, TXFLAG activation can be delayed by adding a damping capacitor between TXMON and GND. Laser Adjustment Procedure The output power from the Laser should be measured with an optical power meter during the setup procedure. In addition TXMON may be monitored to ensure that manufacturers maximum current limits are not exceeded during the set-up process. Select one of the laser drive modes in accordance with the section headed, Optical Operational Modes. in Receive Monitor RXMON and RXFLAG The ACS9020 incorporates a power meter which generates a current source on the RXMON pin, which is proportional to the received signal strength. A voltage is generated on an internal 50Kohm resistor which is continuously compared with an internally generated reference of 1.25 volts. The RXFLAG is set when the RXMON voltage exceeds the 1.25 volt reference. The flag is used to indicate that there is sufficient signal strength to give a minimum differential output signal on the receiver output pins DOUTP and DOUTN. If the voltage on DOUTP/DOUTN exceeds 500 mV peak-to-peak then the RXMON voltage will exceed 1.25 Volts and the RXFLAG will be set. Because of process tolerances on the internal resistor and the internally generated reference voltage, the RXFLAG should be considered only as a guide to the receive signal strength. The receive threshold can be adjusted by placing a 1Mohm external potentiometer between the RXMON pin and Ground. ar y ACS411CS PRE-RELEASE Issue 6.0 July 1999. Transmit monitor TXMON and TXFLAG TXMON is used to monitor the current delivered to the LED or Laser. TXMON is a current source that proportionally mirrors the current flow through the LED or Laser. By placing an appropriate external resistor R TXMON between TXMON and GND, the voltage developed (referenced to GND), will be proportional to the transmit current. During the Laser setup procedure TXMON should be monitored to ensure that the Laser manufacturer's maximum current specification is not exceeded. The transmit current monitor is a current source flowing from VDD out of pin TXMON. This current is representative of the Laser/LED drive current. ITXMON = I BIAS/50 + IMOD/100 IBIAS is the Low level bias current. IMOD is the peak Modulation level bias current. The average modulation current is half this value. Average drive current, I AVG = (IBIAS + IMOD) /2 Therefore I TXMON = IAVG/50 Transmission Clock TCLK There are 16 independent Transmit clocks TCLK(16:1) on the ACS4110. For the purpose of this specification, these signals will be referred to collectively as TCLK. The ACS4110 gives a choice between internally and externally generated transmit clocks. When the CKC pin is held Low, the set of TCLK clocks are configured as outputs producing a clock at the frequency defined by DR(3:1). When the CKC pin is held High, the set of TCLK clocks are configured as inputs, and will accept an externally produced transmission clock with a tolerance of up to 250ppm with respect to the transmission rate determined by DR(3:1). The data appearing on TPOS/TNEG is valid on the rising or falling edge of the TCLK clock dependent on the setting of TRSEL (see Figure 22. Timing diagrams). This is the case for both internally and externally generated transmission clocks. Receive Clock RCLK el im 6 TXMON may also be employed during normal operation to continuously check the Laser current. The voltage developed across R TXMON is compared within an internally generated reference voltage of 1.25V. In the event that the reference voltage is exceeded, the TXFLAG is set High, otherwise it is set Low. In this way, the value of resistor on TXMON can be chosen to activate TXFLAG at any desired transmit current e.g. If RTXMON = 1K, then TXFLAG will be set if I AVG exceeds 62.5mA. Receive Monitor RXMON and RXFLAG The ACS9020 incorporates a power meter which generates a current source which is proportional to the received optical current. There is an internal resistor of value of 50K +/- 20 % connected between RXMON and GND which converts the current into a voltage. RXMON is compared with 1.25V. If RXMON exceeds 1.25V, then output RXFLAG is set = 1, otherwise RXFLAG is set = 0. With the internal resistor of 50K. By adding an external parallel resistor between RXMON and GND, this threshold may be increased. Pr If desired, TXFLAG activation can be delayed by adding a damping capacitor between TXMON and GND. ACS411CS PRE-RELEASE Issue 6.0 July 1999. in There are 16 independent Receive clocks RCLK(16:1) on the ACS4110. For the purpose of this specification, these signals will be referred to collectively as RCLK. The data appearing on RPOS/RNEG is valid on the rising or falling edge of the RCLK clock dependent on the setting of RESEL (see Figure 22. Timing diagrams). To ensure that the average receive frequency is the same as the transmitted frequency, RCLK is generated from a Phase-Lock Loop (PLL) system (except where master mode has been selected). The PLL makes periodic corrections to the output RCLK clock by subtracting or adding a single crystal clock bit-period, so that the average frequency of the RCLK clock tracks the average frequency of the transmit clock of the far-end modem (or system master clock). This decompression/dejittering function is covered in more detail in section headed, Jitter Characteristics. The recovery and de-jittering functions comply to jitter tolerance and jitter transfer specifications of the selected data rates. The algorithm that determines the transfer function and response of the PLLs is modified (shaped) according to the selected data rate. ar y System Frequencies and Clock Generation The crystal clock frequency and the multiplying factors of the MPLL are determined by the choice of data rates. Table 2 lists the required frequencies of the system. Mode Data Rate MHz 16 x T1 16 x E1 7 x T2 4 x E2 1 x E3 1 x T3 1 x OC1 1.544 2.048 6.312 8.448 34.368 44.736 51.840 It is anticipated that most users of the ACS411CS will interface directly with a E1/T1 framers. All the popular framers provide POS/NEG bipolar interfaces which will directly connect to the ACS4110. If required, a detailed description of the AMI/HDB3/ BxZS coding rules are available from Acapella. XTAL MHz 23.160 22.528 23.144 22.528 22.912 22.368 25.920 Fsys MHz 69.480 67.584 69.432 67.584 68.736 67.104 77.760 Data Rate Selection For the purpose of this specification TPN1 represents the set of signals TPOS1 and TNEG1, and RPN1 represents the set of signals RPOS1 and RNEG1. See section headed, Data Coding for a description of the coding types. The maximum recommended crystal (XTAL) is 26.88MHz. An internal multiplier factors the XTAL frequency by 3. The maximum bandwidth is 51.840MHz (OC1). This bandwidth can be utilised in various ways, it may be divided up over 1, 4, 7 or 16 channels. All 16 main channels are completely independent. One channel consists of the following 6 signals: Transmit side: TPOS +ve in bipolar signal or NRZ data TNEG -ve in bipolar signal TPOS TCLK transmit clock (internal or external) Receive side: RPOS +ve in bipolar signal or NRZ data RNEG -ve in bipolar signal or NRZ data RCLK receive clock The data rate can be selected via the data rate selection bits DR(4:1), either directly via pins or via the microprocessor interface. The selection determines the number of active channels in combination with the selected crystal frequency and the line data rate in accordance with Table 4. DR Pins 32 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 TCLK (MHz) 1.544 2.048 6.312 8.448 34.368 44.736 51.840 Nos. of channels 16 16 7 4 1 1 1 Tmode Data Coding NRZ AMI HDB3 B8ZS B6ZS B3ZS NRZ NRZ POL3 POL2 POL1 Table 3: Line coding selection For Non-Return-to-Zero (NRZ) coding, data is applied directly to TPOS inputs, and output data appears only on the RPOS output pins. When using NRZ code, unconnected TNEG input pins will automatically pull-up to VD+. In addition, the ACS411CS will assert a continuous Low on redundant RNEG output pins. AMI, B3ZS, B6ZS, B8ZS and HDB3 coding is normally bipolar. However, it is possible to interface with the ACS411CS using two inputs and outputs rather than a single bipolar interface. Data equivalent to positive excursions of the bipolar AMI/BxZS/HDB3 signal are applied as a logic High to TPOS, while data equivalent to negative excursions are applied as a logic High to TNEG. Similarly, AMI/BxZS/HDB3 positive excursions will appear as a logic High on RPOS and negative excursions will appear as a logic High on RNEG. Pr el im 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 in 7 The main synchronous channels may use any of the following coding methods: NRZ, AMI, HDB3, B3ZS, B6ZS and B8ZS. The desired mode is selected by POL(3:1) input pins, as shown in Table 3. ar Data Coding y Table 2: System frequencies 16 x T1 16 x E1 7 x T2 4 x E2 1 x E3 1 x T3 1 x OC1 Table 4: Data rate and channel selection Channels not used in a specific mode are disabled. For example in 4 x E2 mode channels 1 to 4 are carrying E2 data rates, and channels 5 to 16 are disabled. All channels can be disabled individually via the microprocessor interface, or alternatively via far-end remote control. ACS411CS PRE-RELEASE Issue 6.0 July 1999. Diagnostic modes (main channel) The ACS4110 has four diagnostic/configuration modes implemented for the main channels, configured by CM(3:1). The following diagnostic / configuration modes are implemented for the main channels: - full duplex - full duplex slave - full duplex master - remote loop-back - local loop-back The modes are selectable via CM(3:1) either directly via pins, via the microprocessor interface or via remote control setup. All modes remote loop-back and local loop-back are selectable individually for each channel via the microprocessor interface. Table 5. shows the selection of diagnostic modes and configurations. CM(3:1) 111 110 101 100 011 010 001 000 Diagnostic Mode/Configuration local loop-back initiated from far end (remote setup only) remote loop-back initiated from far end local loop-back remote loop-back full duplex master full duplex slave full duplex slave/remote full duplex (remote setup only) full duplex Table 5: Selection of diagnostic modes All modes are selectable via CM(3:1) either directly via pins or via the microprocessor interface. All the diagnostic modes, including remote loop-back and local loop-back are selectable individually for each main and maintenance channel via the microprocessor interface. Full-Duplex In the full-duplex configuration, the RCLK clock of both devices track the average frequency of the corresponding TCLK clock of the opposite end of the link. The receiving Digital-Phase-Lock Loop (DPLL) system makes periodic adjustments to the RCLK clock to ensure that the average frequency is exactly the same as the far-end TCLK clock. In summary, each TCLK is an independent master clock and each RCLK a slave of the far-end TCLK clock. The relationship between TmCLK and RmCLK are treated similarly. Full-Duplex Slave el im Far End initiate (Remote control device) local loop-back remote loop-back full duplex * full-duplex slave full-duplex master full-duplex full duplex In remote setup (ENRSB=0), the far-end device will be setup complementary to the near-end device (control device) according to the Table 6. CM(3:1) Near End initiate (Control device) 111 110 101 100 011 010 001 000 Pr full duplex * local loop-back remote loop-back full-fuplex master full-duplex slave full-duplex slave full duplex Table 6: Selection of diagnostic modes * Remote Loop-back Detect. For a remote loop-back initiated from the far end device, CM(3:1)=110, the initiating end transmitting and receiving the data will be setup as full duplex (see Figure:1). For remote loop-back, CM(3:1)=100, the remote loopback is initiated from the near end. In both cases, the data that is looped back will be the data applied to the near end device (see Figure:1). ACS411CS PRE-RELEASE Issue 6.0 July 1999. in 8 In slave mode, the TCLK and RCLK clock is derived from the TCLK clock of the far-end modem, such that their average frequencies are identical. Clearly, it is essential that only one modem within a communicating pair is configured in slave mode. The CKC pin should be forced to GND, so that TCLK is always configured as an output. The relationship between TmCLK and RmCLK are treated similarly. The CKM pin should be forced to GND, so that TmCLK is always configured as an output. Full-Duplex Master In master mode, the local RCLK clock is internally generated from the local TCLK clock. The local TCLK clock may be internally or externally generated. Master mode is only valid if the far-end device is configured in slave mode or if the far-end TCLK clock is derived from the far-end RCLK clock. Only one modem within a communicating pair may be configured as a master. The relationship between TmCLK and RmCLK are treated similarly. Local Loopback In local loopback mode, TPN and TmD data is looped back inside the near-end modem and is output at its own RPN and RmD outputs. Data received from the far-end device is ignored, except to maintain lock. If concurrent requests occur for local and remote loopback, local loopback is selected. The local loopback diagnostic mode is used to test data flow up to, and back from, the local ACS4110 and does not test the integrity of the link itself. Therefore, local loopback operates independently of synchronisation with a second modem (i.e. DCD may be High or Low). The local ar y Near-end modem Loop control Near end data looped back TPOS, TNEG, TCLK ACS411CS Far-end modem twin fiber link ACS411CS RPOS, RNEG, RCLK CM(3:1) = 101 local loop-back CM(3:1)=101 Far-end modem data loop back TPOS, TNEG, TCLK Near-end modem Remote loop control* of far end twin fiber link ACS411CS y ACS411CS Figure 1: Local loopback control configurations. *Only if near-end in Remore control mode ENRSB =0 local loop-back initiated by far end modem CM(3:1)=111 Near-end modem Loop control el im ACS411CS CM(3:1) = 100 Near-end modem ACS411CS in twin fiber link twin fiber link CM(3:1) = 111 TPOS, TNEG, TCLK Pr RPOS, RNEG, RCLK Remote loop-back CM(3:1)=100 Far-end modem Loop control Far-end modem looping back data TPOS, TNEG, TCLK RPOS, RNEG, RCLK Remote loop-back initiated by far end modem CM(3:1)=110 Figure 2: Remote loopback control configurations. 9 ar ACS411CS ACS411CS CM(3:1) = 110 RPOS, RNEG, RCLK Far-end modem looping back data ACS411CS PRE-RELEASE Issue 6.0 July 1999. loopback test can be initiated via the microprocessor interface (in all microprocessor modes), giving independent control for each channel. All channels can be simultaneously initiated into local loopback when the microprocessor mode is disabled via the CM(3:1) pins. MSEL(3:1) 101 100 011 010 001 000 Data Rate (kbps) 8 16 32 64 128 256 Remote Loopback In remote loopback mode, both modems are exercised completely, as well as the Lasers/LEDs and the fiber optic link. The remote loopback test is normally used to check the integrity of the entire link from the near-end (initiating modem). Whilst a device is responding to a request for remote loopback from the far-end, requests from the nearend to initiate remote loopback will be ignored. The remote back request can be initiated by either the near end modem (the near-end modem sends a request to the far-end modem to loopback its received data) or by the far end modem itself. In both cases the far end modem loops back the received data to the near end. The remote loopback test can be initiated via the microprocessor interface (in all microprocessor modes), giving independent control for each channel. All channels can be simultaneously initiated into remote loopback when the microprocessor mode is disabled via the CM(3:1) pins. Table 7: Maintenance Channel Data Rate Selection For example: 4 x 16kbps maintenance channels. select MSEL(3:1) = 010, total available bandwidth on TMD1 is 64kbps and frame every 4th bit. The "framing" channel TMD2 is bit locked to the data channel TMD1. Diagnostic Modes and Configuration The diagnostic and configuration modes available for the main channels are also available for the maintenance channels. CM(3:1) also controls the maintenance channels, while all modes including remote loopback and local loopback are also selectable individually via the microprocessor interface. Maintenance channel The ACS4110 offers up to 2 synchronous maintenance channel consisting of the following signals: Transmit Side TMD1 TMD2 TmCLK el im 10 Receive Side RMD1 RMD2 RmCLK Pr transmit NRZ data/framing transmit NRZ data/framing transmit clock (internal or external) receive NRZ data/framing receive NRZ data/framing receive clock Maintenance Data Rate Selection The data rate can be selected via the maintenance data rate selection bits MSEL(3:1), either directly via pins or via the microprocessor interface. TMD1/RMD1 and TMD2/RMD2 support up to 256kbps synchronous data synchronised to TmCLK/RmCLK. They can be used as two independent channels giving a total available bandwidth to 512kbps. Alternatively, TMD1 or TMD2, together with a specific data rate selection, can be used to divide the bandwidth of the remaining maintenance channel into subchannels with a certain data rate, defined in Table 7. ACS411CS PRE-RELEASE Issue 6.0 July 1999. in Transmit and Receive Clock The ACS4110 gives the choice between internally or externally generated TmCLK under the control of the CKM pin. When the CKM pin is held Low, TmCLK is configured as an output producing a clock at the data rate determined by MSEL(3:1). When the CKM pin is held High, TmCLK is configured as an input, and will accept an externally produced transmission clock at the data rate determined by MSEL(3:1). Input data appearing on the TMD1/2 inputs is latched into the device on either the rising or falling edge of the TmCLK clock depending on the setting of TRSEL. This data appears at the RMD1/2 outputs of the farend modem on the rising or falling edge of the RmCLK clock depending on the setting of RESEL (see Figure 21. Timing diagrams). To ensure that the average receive frequency is the same as the transmitted frequency, RmCLK is generated from a Digital Phase-Lock Loop (DPLL) system. Whilst the TMD1/RMD1 and TMD2/RMD2 maintenance channels have a fixed phase relationship with each other, they do not have a fixed phase relationship with the main TPOS/TNEG data transmission channels. ar y TmCLK and the reference clock for the (digital) clock recovery and de-jittering PLLs (DPLL) for RmCLK are derived digitally from the system clock for 256kbps by the division factors shown in Table 8. If lower data rates than 256kbps are selected, the 256kHz clock will be divided down by a factor 2/4/8/ 16/32 determined by MSEL(3:1). Mode 16 x T1 16 x E1 7 x T2 4 x E2 1 x E3 1 x T3 1 x OC1 FSys/256 kbps 271.40625 264 271.21875 264 268.5 262.125 303.75 ERRC and ERRL - Error Detection These signals can be used to give an indication of the quality of the optical link. Even when a DC signal is applied to the data, maintenance and TCLK inputs, the ACS411CS modem transmits data over the link in each direction at the Fsys system frequency. This transmit and control data is used to maintain the timing and synchronisation. The transmit and control data is constantly monitored to make sure it is compatible with the 8B10B format. If a coding error is detected ERRL will go High and will remain High until reset. ERRL may be reset by asserting PORB, or by removing the fiber optic cable from one side of the link thereby forcing the device temporarily out of lock. ERRC produces a pulse on detection of each coding error. These pulses may be accumulated by means of an external electronic counter. In the microprocessor modes, the value on an internal accumulating 8 bit counter can be read via the bus interface address 0x1D. Please note that ERRL and ERRC detect 8B10B coding errors and not data errors, nevertheless because of the complexity of the coding rules employed on the ACS411CS, the absence of detected errors on these pins will give a good indication of a high quality link. Pr el im 11 ACS411CS PRE-RELEASE Issue 6.0 July 1999. in ar y Table 8: System Clock Division Factors for Maintenance Clock Generation (256kbps) Microprocessor Interface Bus Interface Mode Selection The ACS4110 incorporates an 8-bit parallel microprocessor bus interface, which can be configured for the following modes via the bus interface mode control pins UPSEL(3:1) as defined in Table 9. UPSEL(3:1) Mode 111 110 101 100 011 010 001 000 (7) (6) (5) (4) (3) (2) (1) (0) OFF OFF SERIAL MOTOROLA INTEL MULTIPLEXED EPROM OFF Description Interface disabled Interface disabled Serial uP bus interface Motorola interface Intel compatible bus interface Multiplexed bus interface EPROM read mode Interface disabled MULTIPLEXED mode The MULTIPLEXED mode (UPSEL = 2) enables the ACS4110 to interface with a microprocessor using a combined multiplexed address/data bus. The bus interface pins are defined in Table 11. Pin CSB ALE RDB WRB AD(7:0) RDY Dir I I I I IO O Description Active low chip select Address latch enable Active low read enable Active low write enable Address / Data bus Ready Table 11: uP Bus Interface Pins for MULTIPLEXED mode. Table 9: Microprocessor Interface Mode Selection Note: Bit 0 is the least significant bit for all modes used here, and the byte structure complies to little endian format (byte 0 is least significant and stored at lowest address). In OFF Mode, the bus interface is disabled. Control of the device is solely via I/O pins. This will result in limited programmability, as for example individual set-ups for remote loop-back and local loop-back for each channel are not possible, only a collective one. In this mode, all BUS I/O pins are tri-stated or used as additional input pins (ie. POL(3:1), CKLOCAL). ar Pin Dir CSB RDB WRB A(4:0) AD(7:0) RDY I I I I IO O Pin CSB WRB A(4:0) AD(7:0) RDY Dir I I I IO O The INTEL mode (UPSEL = 3) enables the ACS4110 to interface with a Intel 80x86 type microprocessor bus. The bus interface pins used are defined in Table 12. Description in 12 el im Description Table 12: uP Bus Interface Pins for INTEL mode. EPROM mode MOTOROLA mode The MOTOROLA mode (UPSEL = 4) enables the ACS4110 to interface with a Motorola 680x0 type microprocessor bus. The bus interface pins used are defined in Table 13. Description Active low chip select Read / write bar select Address bus Data bus Active low data transfer acknowledge (DTACK) The valid read addresse 0, 0xAA is used to check if a memory device is actually attached to the device. If no memory is attached, the bus interface reverts to the default OFF mode. All other read addresses are not valid. The bus interface pins used in EPROM mode are defined in Table 10. Pin CSB A(4:0) AD(7:0) Dir O O I Pr The EPROM mode (UPSEL = 1) enables the device to read its set-up from a memory device. An internal state machine controls the access to the memory. All addresses in the memory map are read, and the device is set up according to the corresponding data. The access time is scaled to interface with the AMD AM27C020 at lowest speed (250ns) specification. Table 13: uP Bus Interface Pins for MOTOROLA mode. Active low chip select/output enable Address output to EPROM Data input from EPROM Table 10: uP Bus Interface Pins for EPROM mode. ACS411CS PRE-RELEASE Issue 6.0 July 1999. y INTEL mode Active low chip select Active low read enable Active low write enable Address bus Data bus Ready SERIAL mode The SERIAL mode (uPSEL = 5) enables the ACS4110 to interface with a serial microprocessor bus. The bus interface pins are defined in Table 14. Pin CSB ALE A(1) A(0) AD(0) Dir I I I I O Description Active low chip select = SCLK: Serial interface clock = CLKE: Active SCLK edge selection control bit = SDI: Serial data input = SDO: Serial data output The near-end modem has to be setup as the control device (ENRSB=0) in order to configure the far-end by remote control. If both modems are setup as control devices (ENRSB=0), data transmission and reception will be disabled. When in remote setup, the signal CKLOCAL selects whether the Tx/Rx clock settings (CKC, CKM, RESEL, TRSEL, trsel_m and resel_m) should be taken from the controlling device (CKLOCAL=0) or locally (CKLOCAL=1). The diagram in Figure 1 shows the configurations in Remote Control mode. Table 14: uP Bus Interface Pins for SERIAL mode. Remote Control The device setup of one modem can be over-ridden with the device set up from the other modem when remote control is enabled from the ENRSB pin. To enable remote control mode, ENRSB pin is held Low (Logic 0). If a modem is set up in remote control, the data from the control modem overides the local microprocessor interface or pin set-up of the remote controlled modem. The signals that will be over-ridden are defined in Table 15. Name Description ch_enb(16:1) Channel enable defined in local microprocessor for individual channel setup DR(3:1) POL(3:1) CM(2:1) TRSEL RESEL CKM CKC MSEL(3:1) Data rate select Line code polarity select Configuration mode(full-duplex/master/slave) Clock edge select for transmit clocks Clock edge select for receive clocks Clock direction select maintenance channel Clock direction select main channels(combined) Maintenance channel data rate select Remote control is only possible in one direction (only one modem allowed with ENRSB = 0). Pr Table 15: Remote Control Device Setup. el im Control Modem Remote Controlled Modem twin fiber link ACS411CS ACS411CS DR(3:1), MSEL(3:1) CM(3:1), POL(3:1) CKLOCAL=0: CKC, CKM, TRSEL, RESEL CKLOCAL=1: CKC, CKM, TRSEL, RESEL ENRSB = 1 CKLOCAL ENRSB = 0 DR(3:1), MSEL(3:1) CM(3:1), POL(3:1) CKC, CKM, TRSEL, RESEL Figure 3: Remote Control Mode and ENRSB. in 13 ACS411CS PRE-RELEASE Issue 6.0 July 1999. ar y uP Interface timing - MULTIPLEXED mode In MULTIPLEXED mode, the device is configured to interface with a microprocessor using a multiplexed address/data bus. The following figures show the timing diagrams of write and read accesses for this mode. The RDY low time Trdy is at least 2 CLKX cycles after WRB/RDB going low. tpw3 tp1 ALE CSB tsu1 th1 tsu2 WRB tpw1 RDB td1 AD Z address td2 X in data tpw2 th3 Min 5* 0 Typ 60 20 10 * 5* 0 0 0* 60 td3 el im Symbol tsu1 tsu2 td1 Parameter Setup CSB to RDB td2 td3 Delay RDB to RDY td4 td5 tpw1 tpw2 tpw3 th1 th2 th3 tp1 tp2 RDB low time RDY low time ALE high time RDY Setup AD address valid to ALE Delay RDB to AD data valid Delay CSB to RDY active Pr ACS411CS PRE-RELEASE Issue 6.0 July 1999. Delay RDB to AD data High-Z Delay CSB to RDY High-Z Hold AD address valid after ALE Hold CSB low after RDB Hold RDB low after RDY Time between ALE and RDB Time between consecutive accesses (RDB to ALE ) Figure 4: Read access timing in MULTIPLEXED Mode. Note: preliminary timing information. Timing values marked with * TBA. 14 ar th2 td4 X td5 Z Max 10 * 10 * 10 * 10 * 10 * 60 y tpw3 tp1 ALE tsu1 th1 CSB tsu2 tpw1 th2 WRB RDB AD address td1 X td2 tpw2 data th3 X RDY Z Symbol tsu1 tsu2 Parameter in Min 5* 0 10 * 60 20 10 * 5* 0 0 5* 0* 60 Setup AD address valid to ALE Setup CSB to WRB el im tsu3 td1 td2 td3 tpw1 tpw2 tpw3 th1 th2 WRB low time RDY low time ALE high time Setup AD data valid to WRB Delay CSB to RDY active Delay WRB to RDY Delay CSB to RDY High-Z Pr th3 th4 tp1 tp2 Hold AD address valid after ALE Hold CSB low after WRB Hold WRB low after RDY AD data hold valid after WRB Time between ALE and WRB Time between consecutive accesses (WRB to ALE ) Figure 5: Write access timing in MULTIPLEXED Mode. Note: preliminary timing information. Timing values marked with * TBA. 15 ar td3 Typ Max 10 * 10 * 10 * 60 y Z ACS411CS PRE-RELEASE Issue 6.0 July 1999. tsu3 th4 uP Interface timing - INTEL mode In INTEL mode, the device is configured to interface with a microprocessor using a 80x86 type bus. The following figures show the timing diagrams of write and read accesses for this mode. The RDY low time Trdy is at least 2 CLKX cycles after WRB/RDB going low. CSB WRB RDB th1 tsu1 tsu2 A AD RDY Z address td1 data in tpw2 th3 Min 0 0 Typ 60 20 0 0 0 60 td2 Z td3 el im Symbol tsu1 tsu2 td1 Parameter Setup A valid to CSB Setup CSB to RDB Delay RDB to AD valid td2 Delay CSB to RDY active Delay RDB to RDY td3 Pr td4 td5 tpw1 tpw2 th1 th2 th3 tp ACS411CS PRE-RELEASE Issue 6.0 July 1999. Delay RDB to AD High-Z Delay CSB to RDY High-Z RDB low time RDY low time Hold A valid after RDB Hold CSB low after RDB Hold RDB low after RDY Time between consecutive accesses (RDB to RDB or RDB to WRB ) Figure 6: Read access timing in INTEL Mode. Note: preliminary timing information. Timing values marked with * TBA. 16 ar td4 td5 Max 10 * 10 * 10 * 10 * 10 * 60 y Z Z tpw1 th2 CSB tsu1 tsu2 tpw1 th2 WRB RDB A address tsu3 th4 th1 AD td1 td2 tpw2 Z data th3 td3 Symbol tsu1 tsu2 tsu3 td1 td2 td3 Parameter Setup A valid to CSB Setup CSB to WRB Setup D valid to WRB Delay CSB to RDY active Delay WRB to RDY in 10 * 60 20 5* 0 0 5* 60 el im tpw1 tpw2 th1 WRB low time RDY low time th2 th3 th4 Delay CSB to RDY High-Z Hold A valid after WRB Hold CSB low after WRB Hold WRB low after RDY AD hold valid after WRB Pr tp Time between consecutive accesses (WRB to WRB or WRB to RDB ) Figure 7: Write access timing in INTEL Mode. Note: preliminary timing information. Timing values marked with * TBA. 17 ar Min 0 Typ Max 0 10 * 10 * 10 * 60 ACS411CS PRE-RELEASE Issue 6.0 July 1999. y RDY Z uP Interface timing - MOTOROLA mode In MOTOROLA mode, the device is configured to interface with a microprocessor using a 680x0 type bus. The following figures show the timing diagrams of write and read accesses for this mode. The Dtack high time Trdy is at least 2 CLKX cycles after CSB going low. tpw1 CSB tsu2 th2 X tsu1 th1 WRB X A address td1 AD Z td2 tpw2 data RDY (DTACK) Z in th3 td4 Min 0 5* 10 * 10 * 10 * 10 * 60 20 0 5* 0 60 60 Typ Max Pr td4 tpw1 tpw2 th1 th2 th3 tp ACS411CS PRE-RELEASE Issue 6.0 July 1999. Note: preliminary timing information. Timing values marked with * TBA. el im Symbol tsu1 tsu2 td1 Parameter Setup A valid to CSB Delay CSB to AD valid td2 Delay CSB to DTACK td3 CSB low time DTACK high time Hold A valid after CSB Setup WRB valid to CSB Delay CSB to AD High-Z Delay CSB to RDY High-Z Hold WRB high after CSB Hold CSB low after DTACK Time between consecutive accesses (CSB to CSB ) Figure 8: Read access timing in MOTOROLA Mode. 18 ar X td3 Z Z y tpw1 CSB tsu2 th2 X tsu1 th1 X tsu3 th4 X th3 td2 WRB X A address AD X td1 tpw2 data RDY (DTACK) Z Symbol tsu1 tsu2 tsu3 td1 td2 Parameter Setup A valid to CSB Setup WRB valid to CSB Setup AD valid to CSB Delay CSB to DTACK in 10 * 60 20 5* 5* 0 5* 60 el im tpw1 tpw2 th1 th2 CSB low time DTACK high time th3 th4 tp Delay CSB to RDY High-Z Hold A valid after CSB Hold WRB low after CSB Hold CSB low after DTACK Hold AD valid after CSB Pr Time between consecutive accesses (CSB - to CSB ) Figure 9: Read access timing in MOTOROLA Mode. Note: preliminary timing information. Timing values marked with * TBA. 19 ar Min 0 Typ Max 5* 10 * 10 * 60 ACS411CS PRE-RELEASE Issue 6.0 July 1999. y Z uP Interface timing - SERIAL mode In SERIAL mode, the device is configured to interface with a serial microprocessor bus. The following figures show the timing diagrams of write and read accesses for this mode. During read access the output data sdo (AD(0)) is clocked out on the rising edge of SCLK (ALE) when the active edge selection control bit CLKE (A(1)) is 0, and on the falling edge when CLKE is 1. Address, read/write control bit and write data are always clocked into the interface on the rising edge of SCLK. Both input data sdi and clock SCLK are oversampled , filtered and synchronized to the system clock CLKX. The serial interface clock (SCLK) is not required to run when no access is performed (CSB = 1). CSB tsu2 tpw2 th2 ALE = SCLK tsu1 tpw1 A1 A2 A3 A4 A5 A6 ar td1 D0 D1 D2 D3 D4 Min Typ Max 10 * 10 * 10 * 10 * 240 240 20 * 120 250 A(0) = SDI R/W y td2 D5 D6 Z th1 AD(0) = SDO Z Symbol tsu1 tsu2 th1 Parameter Setup SDI valid to SCLK Setup CSB to SCLK Hold SDI to SCLK Pr td2 tp ACS411CS PRE-RELEASE Issue 6.0 July 1999. Note: preliminary timing information. Timing values marked with * TBA. el im th2 Hold SCLK to CSB tpw1 tpw2 td1 SCLK low time SCLK high time Delay SCLK (SCLK for CLKE = 1) to SDO valid Delay CSB to SDO High-Z Time between consecutive accesses (CSB to CSB ) Figure 10: Read access timing in SERIAL Mode. in 20 CSB tsu2 tpw2 th2 ALE = SCLK th1 tsu1 tpw1 A0 A1 A2 Z A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 A(0) = SDI AD(0) = SDO R/W Symbol tsu1 tsu2 th1 th2 tpw1 tpw2 tp Parameter Setup SDI valid to SCLK Setup CSB to SCLK Hold SDI to SCLK Hold SCLK to CSB SCLK low time SCLK high time Min 10 * 10 * 10 * 10 * 240 Typ Max Time between consecutive accesses (CSB to CSB ) Figure 11: Write access timing in SERIAL Mode. Note: preliminary timing information. Timing values marked with * TBA. uP Interface timing - EPROM mode el im address tacc Z data Symbol tacc Parameter Pr In EPROM mode, the ACS4110 takes control of the bus as master, and reads the device set-up from an AMD AM27C020 type EPROM at lowest speed (250ns) after device start-up (system reset). The EPROM access state machine in the up interface sequences the accesses. The following figures show the timing diagrams of the read access for this mode. For a more detailed timing specification, see AMD Am27C020 data sheet, July 1993, p. 2-95. CSB (= OEB) A in If the microprocessor interface is enabled (UPSEL / = 0), the default start-up values are taken over from the pin values as default during reset for the following control pins: CM(3:1) CKC, CKM, TRSEL , RESEL MSEL(3:1), ENRSB DR(3:1) Z Min Typ Max 590 AD Delay CSB or A change to AD valid Figure 12: Read access timing in EPROM Mode. Note: preliminary timing information. Timing values marked with * TBA. 21 ar 240 250 ACS411CS PRE-RELEASE Issue 6.0 July 1999. y Memory Map Table 15 shows the memory map of the ACS4110. The location names are chosen to match the corresponding pin names. Signals not directly equivalent to pins are in lower case. The device identification number id<7:0> on address 0x00 is used in EPROM mode to check if an external memory device is connected. The value to be programmed is 0xAA. The whole chip set-up except DR<3:1> can be controlled individually for each channel. The error counter errc<7:0> (address 0x1D) is an 8-bit saturating counter for the ERRC error pulse. A write of a 0x00 mask to this address clears the counter to 0x00. The status signals ERRL, fail_ne, fail_fe can also be cleared by writing a 0 to the specific bit in the address. For example, writing a mask of 0xDF to address 0x1C clears the ERRL signal, but leaves other status signals unchanged. If the microprocessor interface is enabled (UPSEL /= 0), the default start-up values of all control bits except POL(3:1) and CKLOCAL are taken over from the pin values as default during reset. Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 Bit 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7 6-4 3 2 1 0 7 6-4 3 2-0 7-0 7-0 7-0 7-0 7-2 1 0 7 6 5 4 3 2 1 0 7-0 7-0 7-0 Access R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R/W R/W R/W R R R/W R/W - Name id<7:0> ch_enb<8:1> ch_enb<16:9> cm1<8:1> cm1<16:9> cm2<8:1> cm2<16:9> cm3<8:1> cm3<16:9> pol1<8:1> pol1<16:9> pol2<8:1> pol2<16:9> pol3<8:1> pol3<16:9> ckc<8:1> ckc<16:9> trsel<8:1> trsel<16:9> resel<8:1> resel<16:9> cm_m<3:1> CKLOCAL CKM trsel_m resel_m Description el im rlm_det llm_det DCD LOSS ERRL fail_ne fail_fe resync_ne resync_fe errc<7:0> tm<7:0> Device identification number. Channel enable (active low) for channels 1 to 8. Channel enable (active low) for channels 9 to 16. Configuration mode CM bit 1 for channels 1 to 8. Configuration mode CM bit 1 for channels 9 to 16. Configuration mode CM bit 2 for channels 1 to 8. Configuration mode CM bit 2 for channels 9 to 16. Configuration mode CM bit 3 for channels 1 to 8. Configuration mode CM bit 3 for channels 9 to 16. Line code polarity POL bit 1 for channels 1 to 8. Line code polarity POL bit 1 for channels 9 to 16. Line code polarity POL bit 2 for channels 1 to 8. Line code polarity POL bit 2 for channels 9 to 16. Line code polarity POL bit 3 for channels 1 to 8. Line code polarity POL bit 3 for channels 9 to 16. Clock direction select for channels 1 to 8. Clock direction select for channels 9 to 16. Transmit clock edge select for channels 1 to 8. Transmit clock edge select for channels 9 to 16. Receive clock edge select for channels 1 to 8. Receive clock edge select for channels 9 to 16. Configuration mode CM for maintenance channel. Local Tx/Rx CLK setup in remote control mode Clock direction select maintenance channel. Transmit clock edge select for maintenance channel. Receive clock edge select for maintenance channel. Pr 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F ACS411CS PRE-RELEASE Issue 6.0 July 1999. MSEL<3:1> ENRSB DR<3:1> rl_det<8:1> rl_det<16:9> ll_det<8:1> ll_det<16:9> in Table 15: Memory Map Maintenance channel data rate select. Enable remote control setup. Data rate select. Near-end remote loop-back detect channels 1 to 8. Near-end remote loop-back detect channels 9 to 16. Far-end local loop-back detect channels 1 to 8. Far-end local loop-back detect channels 9 to 16. Near-end remote loop-back detect for maintenance channel. Far-end local loop-back detect for maintenance channel. Data carrier detect status. Loss of signal status. Error latch. Alarm indication for near-end receive fail. Alarm indication for far-end receive fail. Near-end device has entered re-synchronization. Far-end device has entered re-synchronization. 8-bit saturating error counter (reset by write). Test mode select. 22 ar y Laser/LED Considerations Since LEDs or Lasers from different suppliers may emit different wavelengths, it is recommended that the Lasers/LEDs in a communicating pair of modems are obtained from the same supplier. Acapella will assist with contact names and addresses on request. LOSS ( Loss Of Synchronisation) There are two conditions that will make LOSS go to Logic 1. These are: i) Loss of synchronisation - synchronisation windows incorrectly aligned i.e DCD=0. ii) 64 received symbols break the 8B10B encoding rules in a sequence of 256 symbols. In order to return LOSS to the Logic 0 state the following criteria must be met: i) The devices must be synchronised synchronisation windows correctly aligned i.e DCD=1. ii) There are no received symbols in a sequence of 256 symbols which break the 8B10B coding rules. Power Supply Decoupling The ACS9020 contains a highly sensitive amplifier, capable of responding to extremely low current levels. To exploit this sensitivity it is important to reduce external noise to a low level compared to the input signal from the Laser/LED. The modem should have an independent power trace to the point where power enters the board. The Laser/LED should be sited very close to the PMN, PINP, PINN, LAN and LAP pins. A generous ground plane should be provided, especially surrounding the sensitive PINP and PINN tracks from the ACS9020 pins to the optical component. The modem should be protected from EMI/RFI sources in the standard ways. in VB 100nF el im VA+ VD+ pins are 6, 38, 52, 82, 85, 94, 105, 139, 161, 162 VDD ar Place all power supply inductors and decoupling capacitors as close to the ACS9020 device as possible. VDD VDD VDD L = 47 H R < 1 L = 47 H R < 1 L = 47 H R < 1 VD+ Pr GND 100nF ACS4110 GND y 100nF GND 100nF GND GND 100nF GND RXVDD1 RXGND TXGND GND1 GND GND GND GND Place all power supply decoupling capacitors as close to the ACS4110 device as possible. GND pins are 5, 37, 51, 81, 84, 108, 122, 123, 124, 128, 130, 138, 159, 160 100nF GND L = 47 H R < 1 TXVDD 100nF +5V + GND VDD 100 nF GND (GND) 0V 100 F GND pins are 9, 24, 42, 58 Figure 13: Power supply considerations. 23 ACS411CS PRE-RELEASE Issue 6.0 July 1999. GND2 VB PLLVDD VDD ACS9020 (2 off) RXVDD2 VDD Link Budgets The link budget is the difference between the power coupled to the fiber via the transmit Laser/LED and the power required to realise the minimum inputamplifier current via the receive PIN/LED. The link budget is normally specified in dB, and represents the maximum attenuation allowed between communicating Lasers/LEDs. The budget is utilised in terms of the cable length, cable connectors and splices. It usually includes an operating margin to allow for degradation in LASER/LED performance. The power coupled to the cable is a function of the efficiency of the Laser/LED, the current applied to the Laser/LED and the type of the fiber optic cable employed. Twin Fiber LED link (880nm LED + PIN) Link Budget Example (Rtset set so LED launch current = 100 mA peak) Fiber type Glass (multimode) Fiber size 62.5micron Minimum transmit couple power to fiber (W) Minimum PIN responsivity (A/W) Minimum ACS9020 sensitivity (nA) Minimum input power to ACS9020 amplifier (W) 100 0.1 Link budget (dB) (multi mode fiber attenuation = 3 dB/km) el im Twin Fiber LASER link (1310nm Laser and PIN) Link Budget Example (Rtset set so LASER launch current = 25 mA peak) Fiber type Glass (single mode) Fiber size 9 micron Minimum transmit couple power to fiber (W) Minimum PIN responsivity (A/W) Pr Minimum ACS9020 sensitivity (nA) Minimum input power to ACS9020 amplifier (W) Link budget (dB) (single mode fiber attenuation = 0.3 dB/km) Single Fiber LASER link (1310nm and 1510nm WDM device) Link Budget Example (Rtset set so LASER launch current = 25 mA peak) Fiber type Glass (single mode) Fiber size 9 micron Minimum transmit couple power to fiber (W) Minimum PIN responsivity (A/W) Minimum ACS9020 sensitivity (nA) Minimum input power to ACS9020 amplifier (W) Link budget (dB) (single mode fiber attenuation = 0.3 dB/km) 1000 0.8 1500 4 27 Figure 14: Link bugdet examples. ACS411CS PRE-RELEASE Issue 6.0 July 1999. in 1500 20 8.24 1000 0.8 1500 4 27 24 ar y Jitter Characteristics The receive path includes a Phase Locked Loop block, which provides an independent PLL for each transmission channel. The purpose of each PLL is to regenerate the clock signal such that it tracks the transmit clock of the far end modem. The PLL will also attenuate the jitter present in the received data stream. For E1, E2, T1 and T2 modes, the PLL algorithm implemented is entirely digital. For E3, T3 and OC1/ STS1 modes, the PLL block utilised a mixed signal PLL algorithm. The mixed signal PLL does not require the use of external tuning components. The dynamic range of all PLL algorithms is +/- 500ppm. The dynamic range is used to accommodate oscillator frequency differences between the two communicating modems, as well as any jitter and wander present in the received data stream. The jitter characteristics for the ACS4110 is independent of the binary content of the transmitted data stream. T1 Jitter specification When configured for T1 operation, the Jitter Tolerance and Jitter Transfer performance conforms to that specified in AT&T Publication 62411. 1000 100 10 1 0.1 1.0E-01 el im 1.0E+00 1.0E+01 1.0E+00 1.0E+01 in 1.0E+02 1.0E+03 1.0E+04 1.0E+05 T1 Jitter Transfer 1.0E+02 1.0E+03 1.0E+04 1.0E+05 Figure 15: T1 Jitter specifications. Pr 0 1.0E-01 -10 -20 -30 -40 -50 -60 25 ar ACS411CS PRE-RELEASE Issue 6.0 July 1999. y T1 Jitter Tolerance T2 and T3 Jitter specification When configured for T2 operation, the Jitter Tolerance performance exceeds that specified in both ITU-T G.824 and Bellcore GR-499-CORE. When configured for T3 operation, the Jitter Tolerance performance exceeds that specified in both ITU-T G.824 and Bellcore GR-499-CORE. In the absence of input jitter, the output jitter generated from the mixed signal PLL after band pass filtering from 12kHz to 400kHz is 0.07UIpp. T2 Jitter Tolerance 10 1 0.1 0.01 1.0E+01 el im G824 GR-499-CORE 1.0E+02 in 1.0E+03 1.0E+04 1.0E+05 T3 Jitter Tolerance Pr 100 10 1 0.1 G824 GR-499-CORE 0.01 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 Figure 16: T2 and T3 Jitter specifications. ACS411CS PRE-RELEASE Issue 6.0 July 1999. 26 ar y 100 E1 Jitter specification When configured for E1 operation, the Jitter Tolerance performances exceeds that specified in ITU-T G.823. The Jitter Transfer performance exceeds that specified in ITU-T G.736. With reference to ITU-T G.736, section 6.1.3; in the case where the timing signal is derived from an incoming 2048kbit/s signal having no jitter, the output jitter should not exceed 0.10 UIpp when it is measured in the frequency range 20Hz to 100kHz. E1 Jitter Tolerance 10 0.1 1.0E-01 el im 1.0E+00 1.0E+01 1.0E+01 1.0E+02 1 in 1.0E+02 1.0E+03 1.0E+04 1.0E+05 E1 Jitter Transfer 1.0E+03 1.0E+04 1.0E+05 Figure 17: E1 Jitter specifications. Pr 10 0 1.0E+00 -10 -20 -30 -40 -50 -60 27 ar ACS411CS PRE-RELEASE Issue 6.0 July 1999. y 100 E2 Jitter specification When configured for E2 operation, the Jitter Tolerance performance exceeds that specified in ITU-T G.823. In the absence of input jitter, the output jitter generated from the Digital PLL for E2 operation is: Frequency band 20Hz to 400kHz 80kHz to 400kHz Output Jitter 0.7UIpp 0.09UIpp E2 Jitter Tolerance 10 1 0.1 1.0E+00 el im 1.0E+01 1.0E+02 1.0E+01 1.0E+02 in 1.0E+03 1.0E+04 1.0E+05 1.0E+06 E2 Jitter Transfer 1.0E+03 1.0E+04 1.0E+05 1.0E+06 Figure 18: E2 Jitter specifications. ACS411CS PRE-RELEASE Issue 6.0 July 1999. Pr 10 0 1.0E+00 -10 -20 -30 -40 -50 -60 28 ar y E3 Jitter specification When configured for E3 operation, the Jitter Tolerance performance exceeds that specified in ITU-T G.823. Output Jitter Generation after band pass filtering 10 kHz to 800kHz. E3 Jitter Tolerance 10 0.1 1.0E+01 1.0E+02 el im 1.0E+03 1.0E+01 1.0E+02 in 1.0E+04 1.0E+05 1.0E+06 E3 Jitter Transfer 1.0E+03 1.0E+04 1.0E+05 1.0E+06 Figure 19: E3 Jitter specifications. 10 0 1.0E+00 -10 -20 -30 -40 -50 -60 Pr 29 ACS411CS PRE-RELEASE Issue 6.0 July 1999. ar 1 y OC1/STS1 Jitter specification When configured for OC1/STS1 operation, the Jitter Tolerance and Jitter Transfer performance exceeds the requirements specified in Bellcore GR-253-CORE. In the absence of input jitter, the output jitter generated from the mixed signal PLL after band pass filtering from 12kHz to 400kHz is 0.07UIpp. OC1/STS1Jitter Tolerance 100 1 0.1 1.0E+01 el im 1.0E+02 1.0E+03 1.0E+02 1.0E+03 in 1.0E+04 1.0E+05 1.0E+06 OC1/STS1 Jitter Transfer 1.0E+04 1.0E+05 1.0E+06 Figure 20: OC1/STS1 Jitter specifications. 10 0 1.0E+01 ACS411CS PRE-RELEASE Issue 6.0 July 1999. Pr -10 -20 -30 -40 -50 -60 30 ar 10 y twh twl TmCLK and RmCLK clock pulse widths TmCLK RmCLK tsut tht tsur thr TmD1, TmD2 Transmit set-up and hold times The active TmCLK edge is defined by input TRSEL. Figure 21: Timing diagrams twh el im twl tht TPOS/TNEG Figure 22: Timing diagrams 31 in ar tr 90 % 10 % The active RmCLK edge is defined by input RESEL. y RmD1, RmD2 Receive set-up and hold times tf 90 % 10 % Pr TCLK tsut TCLK and RCLK clock pulse widths Digital outputs rise and fall times RCLK tsur t hr RPOS/RNEG Transmit set-up and hold times The active TCLK edge is defined by input TRSEL. Receive set-up and hold times The active RCLK edge is defined by input RESEL. ACS411CS PRE-RELEASE Issue 6.0 July 1999. TmD1 TmD2 TmCLK MSEL(3:1) CM(3:1) DR(3:1) RESEL TRSEL RmD1 RmD2 RmCLK TXDATN TXDATP ENTX RXDATN RXDATP ACS4110 CTXBIAS CTXMOD TXGND GND1 GND2 el VDD 100 nF 10 nF 100 nF 220 1 nF RMODSET RBIASSET 100 nF 100 nF 100 nF CKC CKM CONTX ERRC ERRL DCD LOSS RDY 62K VDD VA+ RXVDD1 RXVDD2 RXVDD1 220 ENRSB UPSEL(3:1) ALE RDB WRB CSB A(4:0) AD(7:0) PLLVDD VDD TXVDD RXVDD2 in 10 nF 10 nF VREF RSET 10 nF CAGC 100K 100nF GND PORB XTI VREF XTAL TXGND GND1 GND2 COFFSET 1 1 1 RSET 10 nF 10 nF 10 nF 10 nF ACS411CS PRE-RELEASE Issue 6.0 July 1999. VDD 100 nF VB 100 nF RXVDD1 PLLVDD VDD RXVDD2 TPOS(16:1) TNEG(16:1) TCLK(16:1) RPOS(16:1) RNEG(16:1) RCLK(16:1) Pr VA+ 100 nF 100 nF RXVDD1 RXVDD2 100 nF 50K 50K Figure 23: Diagram showing ACS9020 and ACS4110 configuration for twin fiber Laser + PIN. Laser VD+ VA+ LAP Fiber PMN LAN TXDATN TXDATP ENTX TXVDD im ACS9020 TX 10K TXMON L = 47 H R < 1 RXVDD2 32 IREF DOUTN DOUTP ENRXB ENTX ENCOFFB COFFP COFFN ACS9020 RX RXMON PINP PINN ar PIN Diode 1M 100nF L = 47 H R < 1 GND RXVDD1 y 100nF L = 47 H R < 1 GND Fiber VB VDD 100nF GND L = 47 H R < 1 XTO VA+ (VDD)+5V + 100nF (GND) 0V 100 F 100 nF GND * configure with a jumper to enable/disable automatic bias power and modulation power regulation. LEDRX PINRX XIN XOUT F(2:0) RPLL ENPLL DINP DINN DOUTP DOUTN IDOUT ICOFF CBTSTRP COFFWIN ENCOFFB ENRXB RXFLAG RXMON COFFP COFFN CAGC COFFSET VN VP PINN PINP MONN MONP BIASFIX MODFIX IBUF SDATAN SDATAP SCLKN SCLKP TXEN TXSEL QUIETRX MONRX = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = el im GND GND GND float GND float GND GND GND float float GND GND GND float GND VDD float TXDATAN float float TXDATAP float ENTX float float float float float float float float GND/VDD* GND/VDD* GND float float float float float GND GND GND 100 nF VDD 100 nF Figure 24: Diagram showing ACS9020 configuration for use with a 3-pin laser. in VA+ 100 nF 100 nF Pr RXVDD1 PLLVDD VDD RXVDD2 RMODSET RBIASSET ar 10 nF RXVDD1 RXVDD2 50K 50K 10 nF LEDRX PINRX XIN XOUT F(2:0) RPLL ENPLL DINP DINN DOUTP DOUTN IDOUT ICOFF CBTSTRP COFFWIN ENCOFFB ENRXB RXFLAG RXMON COFFP COFFN CAGC COFFSET VN VP PINN PINP MONN BIASFIX MODFIX IBUF SDATAN SDATAP SCLKN SCLKP TXEN TXSEL QUIETRX MONRX = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = GND GND GND float GND float GND GND GND float float GND GND GND float GND VDD float TXDATAN float float TXDATAP float float ENTX float float float float float float GND/VDD* GND/VDD* GND float float float float float GND GND GND VA+ 100 nF 100 nF RXVDD1 RXVDD2 100 nF 50K 50K RXVDD1 PLLVDD VDD RXVDD2 RMODSET RBIASSET Laser LAP Fiber TXDATAN TXDATAP ENTX VDD 100 nF ACS9020 CTXMOD RXGND TXGND GND1 GND2 RSET MONP LAN TXVDD CTXBIAS 10 nF 10 nF When employing a 4-pin Laser, the MONN pin is connected to the cathode of the laser's pin-monitor diode VREF TXDATAN TXDATAP ENTX y LED LAP Fiber LAN TXFLAG TXMON 10K 10 nF 10 nF TXFLAG TXMON 10K ACS9020 CTXMOD RXGND TXGND GND1 GND2 RSET TXVDD CTXBIAS * configure with a jumper to enable/disable automatic bias power and modulation power regulation. Figure 25: Diagram showing ACS9020 configuration for LED transmission. 33 ACS411CS PRE-RELEASE Issue 6.0 July 1999. 10 nF 10 nF VREF Figure 26: Diagram showing ACS9020 configuration as a trans-impdeance-amplifier/post-amplifier. LEDRX PINRX XIN XOUT F(2:0) RPLL ENPLL DINP DINN ICOFF CBTSTRP COFFWIN PINN PINP BIASFIX MODFIX IBUF SDATAN SDATAP SCLKN SCLKP TXEN TXSEL QUIETRX MONRX PMN MONN LAP LAN CTXMOD CTXBIAS RMODSET RBIASSET TXP TXN TXFLAG TXMON IDOUT = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = el im GND GND GND float GND float GND GND GND GND GND float float float VDD VDD GND float float float float float GND VDD GND float float float float float float float float GND GND float float GND VDD 100 nF in 100 nF VA+ 100 nF RXVDD1 Pr RXVDD1 100 nF PLLVDD VDD TXVDD RXVDD2 RXVDD2 ar 10 nF 10 nF 10 nF LEDRX PINRX XIN XOUT F(2:0) RPLL ENPLL DINP DINN ICOFF CBTSTRP COFFWIN VN VP BIASFIX MODFIX IBUF SDATAN SDATAP SCLKN SCLKP TXEN TXSEL QUIETRX MONRX PMN MONN LAP LAN CTXMOD CTXBIAS RMODSET RBIASSET TXP TXN TXFLAG TXMON IDOUT = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = GND VDD GND float GND float GND GND GND GND GND float float float VDD VDD GND float float float float float GND VDD GND float float float float float float float float GND GND float float GND RXVDD1 100 nF 100 nF VA+ 100 nF RXVDD1 100 nF PLLVDD VDD TXVDD RXVDD2 RXVDD2 VDD PIN Diode PINP PINN Fiber 1M DOUTN DOUTP 220 220 DOUTN DOUTP ENRXB ENTX ENCOFFB COFFP ACS9020 COFFSET TXGND GND1 GND2 RXGND CAGC COFFN VREF RSET 10 nF DOUTN DOUTP 220 220 DOUTN DOUTP ENRXB ENTX ENCOFFB COFFP y PIN Diode with integrated TIA CACoup RXMON RXFLAG 1 nF VP VN CACoup Fiber ACS9020 RXMON RXFLAG COFFSET VREF RSET 1M C ACoup = 1 nF COFFN TXGND GND1 GND2 RXGND CAGC 1 nF 10 nF 10 nF Figure 27: Diagram showing ACS9020 configuration as a post-amplifier. ACS411CS PRE-RELEASE Issue 6.0 July 1999. 34 10 nF 10 nF Pr 1 LEDRX 2 PINRX 3 XIN 4 XOUT 5 F0 6 F1 7 F2 8 PLLVDD 9 GND2 10 RPLL 11 ENPLL 12 DINP 13 DINN 14 DOUTP 15 DOUTN 16 IDOUT 17 ICOFF 18 CBTSTRP 19 COFFWIN 20 ENCOFFB 21 ENRXB 22 RXFLAG 23 RXMON 24 RXGND 25 RXVDD1 26 RXVDD2 27 COFFP 28 COFFN 29 CAGC 30 COFFSET 31 RSET 32 VREF ACAPELLA ACS9020 2-Fiber Modem RES = Reserved, IC = Internally Connected Figure 28: Top view of 64 pin TQFP package. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 MONRX QUIETRX TXSEL ENTX TXEN VDD GND1 SCLKP SCLKN SDATAP SDATAN IBUF TXMON TXFLAG TXN TXP MODFIX BIASFIX RBIASSET RMODSET CTXBIAS CTXMOD TXGND LAN LAP TXVDD MONN PMN PINP PINN VP VN el im 35 in ar y ACS411CS PRE-RELEASE Issue 6.0 July 1999. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 TPOS7 TNEG7 RCLK6 RPOS6 GND VD+ RNEG6 TCLK6 TPOS6 TNEG6 RCLK5 RPOS5 RNEG5 TCLK5 TPOS5 TNEG5 RCLK4 RPOS4 RNEG4 TCLK4 TPOS4 TNEG4 RCLK3 RPOS3 RNEG3 TCLK3 TPOS3 TNEG3 RCLK2 RPOS2 RNEG2 TCLK2 TPOS2 TNEG2 RCLK1 RNEG1 GND VD+ RPOS1 TCLK1 TPOS1 TNEG1 RCLK10 RPOS10 RNEG10 TCLK10 TPOS10 TNEG10 RCLK11 RPOS11 GND VD+ RNEG11 TCLK11 TPOS11 TNEG11 RCLK12 RPOS12 RNEG12 TCLK12 TPOS12 TNEG12 RCLK13 RPOS13 RNEG13 TCLK13 TPOS13 TNEG13 RCLK14 RPOS14 RNEG14 TCLK14 TPOS14 TNEG14 RCLK15 RPOS15 RNEG15 TCLK15 TPOS15 TNEG15 GND VD+ TCLK16 GND VD+ RCLK16 RPOS16 RNEG16 1 Pr ACS411CS PRE-RELEASE Issue 6.0 July 1999. el im RES = Reserved, IC = Internally Connected Figure 29: Top view of 176 pin TQFP package. in 2-Fiber Modem 36 ACAPELLA ACS4110 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 TCLK7 RNEG7 RPOS7 RCLK7 TNEG8 TPOS8 TCLK8 RNEG8 RPOS8 RCLK8 TNEG9 TPOS9 TCLK9 RNEG9 VD+ VD+ GND GND RPOS9 RCLK9 TmCLK RmCLK TPOS16 TNEG16 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 A4 A3 A2 A1 A0 VD+ GND RDY CSB WRB RDB ALE ENTX DCD GND PORB GND UPSEL1 UPSEL2 UPSEL3 GND GND GND XTO XTI DR1 DR2 DR3 RESEL VA+ IREF CM1 CM2 CM3 RXDATN RXDATP GND TXDATN TXDATP VD+ TRSEL CKC CKM MSEL1 MSEL2 MSEL3 ENRSB CONTX TmD2 TmD1 VD+ RmD2 RmD1 LOSS ERRL ERRC ar y Pin Description ACS4110 part 1. Pin 6,38, 52,82, 85,94, 105,139, 161,162 Sym IO Name Description Pin Description ACS4110 part 2. Pin 36 31 25 19 13 7 175 169 163 45 53 59 65 71 77 88 Sym RNEG1 RNEG2 RNEG3 RNEG4 RNEG5 RNEG6 RNEG7 RNEG8 RNEG9 RNEG10 RNEG11 RNEG12 RNEG13 RNEG14 RNEG15 RNEG16 IO Name Description VD+ - +ve power supply Power supply, 4.75 - 5.25 Volts. 115 VA+ - +ve power supply Power supply for Clock Recovery PLL, 4.75 - 5.25 Volts. O Receive Data Negative Receive channel 1-16, corresponds to -ve in bipolar signal. 5, 37, 51,81, 84,108, 122,123, 124,128, 130,138, 159,160 41 33 27 21 15 9 1 171 165 47 55 61 67 73 79 154 42 34 28 22 16 10 2 172 166 48 56 62 68 74 80 153 39 30 24 18 12 4 174 168 158 44 50 58 64 70 76 87 GND - Ground Power Supply Pr TNEG1 TNEG2 TNEG3 TNEG4 TNEG5 TNEG6 TNEG7 TNEG8 TNEG9 TNEG10 TNEG11 TNEG12 TNEG13 TNEG14 TNEG15 TNEG16 el im Transmit channel 1-16, corresponds to -ve in bipolar signal. Receive channel 1-16, corresponds to +ve in bipolar signal. TPOS1 TPOS2 TPOS3 TPOS4 TPOS5 TPOS6 TPOS7 TPOS8 TPOS9 TPOS10 TPOS11 TPOS12 TPOS13 TPOS14 TPOS15 TPOS16 ar 120 121 XTI/ XTO 129 PORB I 156 TmCLK I/O 155 RmCLK O 116 RESEL I 104 TRSEL I 95 TmD1 I 92 RmD2 O y System Clock Crystal Power On Reset Transmit maintenance CLK Receive maintenance Clock Receive Edge Select Transmit Edge Select Transmit maintenance Data Receive maintenance Data 131 DCD O Data Carrier Detect When DCD=1, then the communicating modems have synchronised, and are communicating. Connect fundamental parallel resonance crystal with appropriate padding capacitor to GND. Will initialise the device when PORB= 0. PORB is normally connected to an RC circuit so that a POR is automatically invoked on power-up. PORB= 1 for normal operation. Transmit maintenance Clock. samples TmD on edge selected by TRSEL control. I Transmit Data Positive Transmit channel 1-16, corresponds to +ve in bipolar signal. in I Transmit Data Negative O Receive Data Positive Receive maintenance Clock. samples RmD on edge selected by RESEL control.. When RESEL = 1, RPOS/RNEG and RmD data is valid on the rising edge of RCLK/RmCLK. When RESEL = 0, the data is valid on the falling edge of RCLK/RmCLK. When TRSEL = 0, TPOS/TNEG and TmD data is latched on the falling edge of TCLK/TmCLK. When TRSEL =1, the data is latched on the rising edge of TCLK/TmCLK. NRZ maintenance channel. TmD is sampled on the TmCLK clock edge defined by TRSEL. NRZ maintenance channel. RmD is sampled on the RmCLK clock edge defined by RESEL. RPOS1 RPOS2 RPOS3 RPOS4 RPOS5 RPOS6 RPOS7 RPOS8 RPOS9 RPOS10 RPOS11 RPOS12 RPOS13 RPOS14 RPOS15 RPOS16 37 ACS411CS PRE-RELEASE Issue 6.0 July 1999. Pin Description ACS4110 part 3. Pin 40 32 26 20 14 8 176 170 164 46 54 60 66 72 78 83 35 29 23 17 11 3 173 167 157 43 49 57 63 69 75 86 113 112 111 Sym TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 TCLK8 TCLK9 TCLK10 TCLK11 TCLK12 TCLK13 TCLK14 TCLK15 TCLK16 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 RCLK9 RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 RCLK16 CM1 CM2 CM3 IO Name Description Pin Description ACS4110 part 4. Pin Sym IO Name Description When LOSS = 1, receive data is unreliable. When LOSS = 0, receive data is reliable. NRZ maintenance channel. TmD is sampled on the TmCLK clock edge defined by TRSEL. NRZ maintenance channel. RmD is sampled on the RmCLK clock edge defined by RESEL. The MSEL(3:1) input select the Data Rates of channels. See section headed Maintenance Data Rate Selection. Remote device setup. 91 LOSS O LOSS of Signal I/O Transmit clocks Transmit Clock 1-16, samples TPOS/TNEG data on clock edge selected by input TRSEL. 96 TmD1 I Transmit maintenance Data 93 RmD2 O Receive maintenance Data 101 100 99 MSEL1 MSEL2 MSEL3 I Maintenance channel data rate selection Enable Remote Setup 98 ENRSB O Receive clocks Receive Clock, RPOS/RNEG data is valid on edge selected by input RESEL. Pin description ACS4110 part 5 - uP interface. Pin Sym IO Name Description in 133 134 135 136 137 140 141 142 143 144 145 146 147 148 149 150 151 152 A0 A1 A2 A3 A4 ar 127 126 125 UPSEL1 UPSEL2 UPSEL3 I ALE I RDB I WRB I CSB IO RDY O IO AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 IO y I uP Interface uP Interface uP Interface uP Interface uP Interface uP Interface uP Interface uP Interface uP interface mode control. I Configuration Modes el im If errors are detected in the 8B10B coding rules ERRL will be forced high.. ERRL will be reset low if the device is forced out of synchronisation e.g. PORB = 0. ERRC will go high coincident with each error detected in the 8B10B coding rules. Errors may be accumulated by means of an external electronic counter. The DR(3:1) input select the Data Rates and number of channels. See section headed Data Rate Selection. When CKC = 0, TCLK1-16 are configured as an output. When CKC = 1, TCLK1-16 are configured as an input. When CKM = 0, TmCLK is configured as an output. When CKM = 1, TmCLK is configured as an input A 51K 1% resistor should be placed between IREF and GND. CM(3:1) select the Configuration Modes such as full duplex, master and slave mode. uP bus address latch enable. 1) POL3 in pin control mode UPSEL(3:1) = 0. uP bus read (active low). 2) POL2 in pin control mode UPSEL(3:1) = 0. uP bus write (active low). 3) POL1 in pin control mode UPSEL(3:1) = 0. uP bus chip select (active low). 4) CKLOCAL in pin control modeUPSEL(3:1) = 0. uP bus ready/data acknowledge. 90 ERRL O Error Latch 89 ERRC 119 118 117 DR1 DR2 DR3 Pr O Error count I Data Rate Select uP bus address. 103 CKC I Clock Select uP bus address/data. 102 CKM I Clock Select 97 CONTX I Continuous transmit Current reference 114 IREF I ACS411CS PRE-RELEASE Issue 6.0 July 1999. 38 Pin Description of interface signals between ACS9020 and ACS4110. Pin 132 61 Sym ENTX IO O I Name Enable Transmit Description Transmit active (ACS4110). Enable transmit (ACS9020). Negative differential receive data in (or slicing level in for RXDATP). Positive receive data in. Negative differential transmit data in (or slicing level in for TXDATP). Positive transmit data out. Pin Description ACS9020 part 1. Pin 1 2 3 4 5 6 7 8 9 10 Sym LEDRX PINRX XIN XOUT F0 F1 F2 PLLVDD GND2 RPLL IO I I Name LED receive PINP/PINN Receive System Clock Crystal Description Set Logic High or Low. Set Logic High or Low. External crystal with 20pF padding capacitor. 110 RXDATN I Receive data - 109 RXDATP I Receive data I Frequency set PLL rate select. 107 TXDATN O Transmit data 106 TXDATP O Transmit data - VDD for VCO GND PLL reference resistor Power supply, 4.75 - 5.25 Volts. Power supply. 62K to GND 11 ENPLL y I PLL Enable I PLL Positive input data PLL Negative input data I O Receiver Positive output data Receiver Negative output data Reference current for Data output Bias current for automatic offset compensation windowing Auto offset compensation bootstrap capacitor Auto output generated window output Receiver offset compensation enable Receiver enable Receiver signal monitor flag Receiver signal monitor Ground Receive power supply O O I I O - Set Logic High or Low. ar 12 DINP 13 DINN Connect to DOUTN. Connect to DOUTP. in 14 DOUTP Connect to DINN (220 to GND if IDOUT floating). el im Pr 39 15 DOUTN Connect to DINP (220 to GND if IDOUT floating). 16 IDOUT 1K to VDD (or float if using external differential o/p loads). 17 ICOFF 100K to RXVDD1 to give COFFWIN delay of 60ns. 18 CBTSTRP 10nF to GND to give 2ms bootstrap delay (ICOFF = 100K). 19 COFFWIN Connect to ENCOFFB for auto windowing. 20 ENCOFFB Connect o COFFWIN for auto windowing. 21 ENRXB Set to Logic High or Low. Use to drive external monitor LED. 1M potentiometer to GND to adjust RXFLAG threshold. Power supply. Power supply, 4.75 - 5.25 Volts. 22 RXFLAG 23 24 25 RXMON RXGND RXVDD1 ACS411CS PRE-RELEASE Issue 6.0 July 1999. Pin Description ACS9020 part 2. Pin 26 Sym RXVDD2 IO Name Pre-amp power supply Post amp offset capacitor Post amp offset capacitor Preamp AGC capacitor Preamp offset capacitor Receiver current bias resistor Bandgap reference Postamp negative input Postamp positive input Receiver PIN cathode Receiver PIN anode Monitor PIN anode Monitor PIN cathode Description Power supply, 4.75 - 5.25 Volts. Pin Description ACS9020 part 3. Pin 49 Sym TXP IO I Name Data transmit positive Data transmit negative Transmit current monitor flag Transmit monitor current Current reference for SDATA and SCLK drivers Re-synchronised negative data Description Positive output of TX data source. Negative output of TX data source. Used to drive external indicator LED. 27 COFFP - 1nF to COFFN. 50 TXN I 51 1nF to COFFP. TXFLAG O 28 COFFN - 29 CAGC - 10nF to GND. 52 TXMON - 10K potentiometer to GND to adjust TXFLAG threshold. 30 COFFSET - 10nF to GND. 53 10nF to GND. 54 SDATAN IBUF - 470 resistor to VDD (or float if using external differential o/p loads. Re-synchronised negative data output (120 to GND if IBUF floating). Re-synchronised positive data output (120 to GND if IBUF floating). PLL recovered clock negative (120 to GND if IBUF floating). PLL recovered clock positive (120 to GND if IBUF floating). Power supply. Power supply, 4.75 - 5.25 Volts. Connect to ENTX if using internal packet data generator. Set Logic High or Low or to TXEN. Set Logic High or Low. 31 RSET - 33 VN - Negative output from external TIA. Positive output from external TIA. Laser/LED PIN cathode. 34 VP - 35 PINN - in 57 58 59 60 61 62 63 64 el im Laser monitor PIN anode. Laser monitor PIN cathode. Power supply, 4.75 - 5.25 Volts. Laser/LED anode. Laser/LED cathode. Power supply. Laser/LED modulation current set smoothing capacitor 10nF to GND. Laser/LED bias current set smoothing capacitor 10nF to GND. Laser/LED modulation current set resistor 50K potentiometer to GND. Laser/LED bias current set resistor 50K potentiometer to GND. Set Logic High or Low. Set Logic High or Low. 36 PINP - Laser/LED PIN anode. 37 PMN - 38 MONN - 39 40 41 42 TXVDD LAP LAN - Power Supply Anode Cathode - Pr Ground TXGND ar 55 SDATAP O 56 SCLKN O SCLKP O GND1 VDD Ground TXEN O ENTX I Enable transmit TXSEL I QUIETRX 32 VREF - 10nF to GND. y O Re-synchronised positive data PLL recovered clock negative PLL recovered clock positive Power supply Logic transmit window enable Select packet transmit Quiet reception Monitor PIN receive select I I Set Logic High or Low. 43 CTXMOD - Laser/LED modulation MONRX Set Logic High or Low. 44 CTXBIAS - Laser/LED bias 45 RMODSET - Laser/LED modulation 46 RBIASSET - Laser/LED bias Laser/LED bias fix Laser/LED modulation current fix 47 BIASFIX I 48 MODFIX I ACS411CS PRE-RELEASE Issue 6.0 July 1999. 40 xti xto XTAL OSC iref porb PLL rclk1 rpos1 LINE CODER rneg1 P2S MULT PLL CLOCK + RESET GENERATION RX FIFO rxdatp rxdatn DATA SLICER REC PLL S2P 8B10B DEC PLL RX AND LOCK CONTROL P2S 16x PLL rclk16 rpos16 LINE CODER rneg16 rmclk y P2S S2P LINE DEC S2P LINE DEC S2P loss dcd errl errc rmd1 rmd2 tclk1 tpos1 tneg1 tclk16 tpos16 tneg16 tmclk tmd1 tmd2 txdatp txdatn DIFF. DRIVER P2S 8B10B CODER el im uP / MEMORY INTERFACE Pr upsel<2:1> ad<7:0> a<3:0> csb ale wrb rdb rdy Figure 30: Block diagram for ACS4110. in TX FIFO entx TX CONTROL 41 ar 16x MODE CONTROL / STATUS ACS411CS PRE-RELEASE Issue 6.0 July 1999. Thin Quad Flat Pack dimensions in mm Pr el im E1/D1 A A1 A2 0.05 14.00 max min 1.60 0.15 0.05 24.00 max 1.60 0.15 1.45 1.45 1.35 0.50 0.27 0.75 7o 1.35 0.80 0.45 0.17 0.75 0.45 7o 0o 26.00 0.10 in e b 0.30 ar L 0.45 y 0o 16.00 0.10 E/D Copl. min TQFP64 TQFP176 Figure 31: Package information for the 64 and 176 pin TQFP packages. ACS411CS PRE-RELEASE Issue 6.0 July 1999. 42 Pr Acapella Ltd. Delta House Chilworth Research Centre Southampton S016 7NS United Kingdom el im 43 in UK Tel. UK Fax. Intn'l. Tel. Intn'l. Fax. 023 80 769 008 023 80 768 612 +44 23 80 769 008 +44 23 80 768 612 Email: sales@acapella.co.uk Web: www.acapella.co.uk Acapella - a wholly owned subsidiary of This is a pre-released version of the specification. Since the specification is likely to change in response to customer feedback, please check with Acapella that you have the latest version of the specification. In the interest of further product development Acapella reserve the right to change this specification without further notice. (c) Copyright, Acapella Ltd. 1999 ACS411CS PRE-RELEASE Issue 6.0 July 1999. ar y |
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